Standing on the shoulders of giants.

Most folks realize that IBM, DEC, and several other old-school computer manufacturers were thoroughly exploring virtualization around the time my generation was thoroughly exploring our mothers' wombs. Working at VMware for the last six years, I've been constantly aware that much of the ground we're covering was well-worn decades ago. Still, at times, the fidelity of the echos through the generations amazes me.

I've written a lot here about VT, Intel's recently shipped CPU virtualization hardware. I'm pretty intimately familiar with VT's gory guts, as well as those of AMD's Pacifica, after spending a good chunk of my career at VMware extending our VMM to support them. (Sorry to disappoint, AMD/Intel fanboys: the two specifications are pretty much exactly the same, with different instructions and in-memory layouts, etc.)

I was also faintly aware that IBM had done some work to accelerate virtualization "back in the day." But, I was utterly shocked at the familiarity of this paper (Osisek, Jackson, Gum, in IBM Systems Journal, March, 1991). It describes interpretive execution, which is IBM's name for the S/390 virtualization acceleration hardware. What's fascinating is that "interpretive execution" so closely resembles Pacifica, and in turn VT, that you can mechanically translate among them.

What VT calls "non-root mode", and Pacifica calls "guest mode", is known as "interpretive execution" (which, by the way, joins a long list of nuttily technical-sounding, yet completely non-descriptive terms that I associate with IBM; it's right up there with "translation lookaside buffer"). VT's "vmlaunch" instruction is Pacifica's "vmrun" is s/390's Germanic-flavored "sie"; Intel's "VMCS" is AMD's "VMCB" is IBM's "state description" (another hilarious IBM-ism).

The paper also provides something of a crystal ball, describing some interesting extensions that haven't made their way into the x86 vendors' hardware just yet: hardware support for a second level of address translation to support the paged MMU within the guest (which is described, albeit briefly, in the Pacifica spec), hardware SMP guest support (though this might be IBM-specific; it seems to be oriented towards implementing a semi-magical "tlb shootdown" instruction that has no analog on the x86); and I/O acceleration (though again, who knows how applicable this will be to the modern world; the described facilities seem oriented entirely towards pass-through of physical devices, and then only for a single, blessed guest on a given host, which, as Xen demonstrates, can already be implemented today). Everything old is new again...